1. Field of the Invention
The present invention relates to a digital-to-analog (D/A) converter, which is applicable to a liquid crystal display drive circuit or the like that generates a voltage in response to a digital signal to drive a liquid crystal display device.
2. Description of the Background Art
Reference is first made to FIG. 2, which is a schematic block diagram showing a conventional digital-to-analog converter disclosed by U.S. Pat. No. 6,556,162 to Brownlow et al. The digital-to-analog converter is a two-stage conversion system that comprises a first-stage converter section 1 and a second-stage converter section 2. The first-stage converter section 1 selects, according to the m most significant bits (MSBs) in the digital signal DI of k (=m+n) bits, a pair of adjacent voltages from the voltages of 0 to 2m. The first-stage converter section 1 then outputs the selected voltages as an upper voltage limit VH and a lower voltage limit VL. The second-stage converter section 2 divides the voltage between the upper voltage limit VH and the lower voltage limit VL into 2n segment voltages which are equal to each other. The second-stage converter section 2 then selects one of the segment voltages according to the n least significant bits (LSBs) in the digital signal DI.
The second-stage converter section 2 comprises: a resistive voltage divider 3 which divides the voltage between the upper limit voltage VH and the lower limit voltage VL into the 2n equal segment voltages; a switch group 4 which selects one of the 2n segment voltages to output the selected one; and a decoder (DEC) 2a which decodes the n bits to turn on a corresponding switch of the switch group 4.
To the output of the second-stage converter section 2, i.e., to the output of the switch group 4, a capacitive load CL such as a liquid crystal display device is connected via an output buffer including a voltage-follower-connected operational amplifier (OP) 5.
In the digital-to-analog converter, the first-stage converter section 1 selects, in response to the MSB bit in the digital signal DI, a pair of adjacent voltages VH and VL from the voltages of 0 to 2m provided by the low-impedance reference voltage source. The second-stage converter section 2 selects a voltage specified by the LSB bit in the digital signal DI from the 2n equal segment voltages divided from the voltage between the voltage limits VH and VL.
In the above-described digital-to-analog converter, however, the voltages of 0 to 2m that are provided to the first-stage converter section 1a are generated generally by a resistive voltage divider having lower resistance. Between the voltages VH and VL outputted from the first-stage converter section 1 connected in parallel is the resistive voltage divider 3 of the second-stage converter section 2. Smaller resistance of the resistive voltage divider 3 may therefore vary the voltages VH and VL, providing inaccurate analog voltages. The liquid crystal display device or the like will require as many digital-to-analog converters as the number of display electrodes to be connected in parallel with the resistive voltage divider having lower resistance. A plurality of digital-to-analog converters operating at the same time may cause the reference voltage to vary more significantly.
Larger resistance of the resistive voltage divider 3 may increase the time constant of the integrator circuit. The time constant comes from the combination of that resistance with the input capacitance of the operational amplifier 5. A larger time constant may provide a lower response speed, which causes the display device not to follow the fast motion of a displayed image.